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崗位職責(zé):1.負(fù)責(zé)開(kāi)發(fā)在不同制程及工具軟件上的數(shù)字邏輯單元的時(shí)序功耗模型。2.負(fù)責(zé)在較短的時(shí)間內(nèi)，在先進(jìn)的制程中提供標(biāo)準(zhǔn)邏輯的開(kāi)發(fā)流程和設(shè)計(jì)方法，以滿足高質(zhì)量、高精度的要求。1. Library/IP circuits design, pre/post simulation, characterization for Standard Cell, Standard I/O, SRAM, ROM, Emb-Flash, EEPROM, and other special mixed-signal/analog IP etc. 2. Work closely with layout engineer. Provide the guideline and help for physical layout floor plan, design, verification and RC extraction. 3. Wafer or package chip testing and debug. 4. Customer support. 任職資格:1.微電子、計(jì)算機(jī)科學(xué)、電子科學(xué)與技術(shù)等相關(guān)領(lǐng)域知識(shí)的碩士含以上人員。2.熟悉PPA的優(yōu)化數(shù)字邏輯電路和晶體管級(jí)電路設(shè)計(jì)知識(shí)3.具有數(shù)字邏輯電路分析與表征的經(jīng)驗(yàn)4.熟悉經(jīng)驗(yàn)驗(yàn)證/ FineSim模擬包括一些統(tǒng)計(jì)分析工具熟悉Verilog、Synthesis 和STA知識(shí)熟悉腳本語(yǔ)言，如Perl或者Python /殼/ TCL等1. Good knowledge of circuits design. Experience in Std. Cell, I/O, ESD SRAM, memory compiler, non-volatile memory, charge pump, band gap and other mixed-signal/analog IP preferred. 2. Experience in Cadence/Synopsys/Mentor/Springsoft circuit and layout design/simulation/verification tools preferred. 3. Unix/Lunix system experience and Good programming skills preferred, such as C, Perl, TCL etc. 4. Device/Process/Layout/Testing related experience preferred. 5. Intelligent and excellent analysis capability. 6. Self-motivated and hard work. 職能類別：集成電路IC設(shè)計(jì)/應(yīng)用工程師半導(dǎo)體技術(shù) 關(guān)鍵字：半導(dǎo)體ICStd.CellI/OTSMC臺(tái)積電