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崗位職責:Job Description: ：1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.2. Design flow/methodology development and innovation for front-end design challenges.3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips. 任職資格:職位要求：1. MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.2. 3 years working experience.3. Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.4. Familiar with tcl/Perl/Python program. 職位要求：1. 電子、計算機等相關專業，碩士及以上學歷的應屆畢業生。2. 具備基本RTL讀寫與仿真能力。3. 熟悉使用一種或多種IC前端工具（綜合、可測性設計、存儲器內建自測試、形式驗證、靜態時序分析）者優先。4. 具備數字集成電路設計背景和熟悉靜態時序分析者優先。5. 熟悉TCL/Perl/Python一種或多種者語言者優先。 職能類別：數字前端工程師