應屆畢業生
本科
2026-03-05 18:09:01
1107人關注
職位描述
該職位還未進行加V認證，請仔細了解后再進行投遞！
工作職責：
1. Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2. Work on the physical verification (DRC/LVS/Antenna ...)
3. Work on test chip layout design and verification
4. Close cooperation with designers on PPA optimization
任職要求：
1. At least BS Degree of Microelectronics or Physics.
2. Excellent graduate or at least 1 years related working experience
3. Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
4. Familiar with design rule and layout effect in advanced process.
5. Excellent skills of communication and teamwork are also expected.
6. Programming experience (Perl/tcl skill) will be a plus.
7. Experience in advanced process (n16 and beyond) will be a plus.
1. Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2. Work on the physical verification (DRC/LVS/Antenna ...)
3. Work on test chip layout design and verification
4. Close cooperation with designers on PPA optimization
任職要求：
1. At least BS Degree of Microelectronics or Physics.
2. Excellent graduate or at least 1 years related working experience
3. Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
4. Familiar with design rule and layout effect in advanced process.
5. Excellent skills of communication and teamwork are also expected.
6. Programming experience (Perl/tcl skill) will be a plus.
7. Experience in advanced process (n16 and beyond) will be a plus.
注：聯系我時，請說是在江蘇人才網上看到的。
工作地點
地址：南京浦口區臺積電
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職位發布者
孫丹HR
臺積電(中國)有限公司
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電子技術·半導體·集成電路
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500-999人
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股份制企業
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上海市松江區廣富林路1188號
